Wafer Architect
Hybrid Remote/SF Bay Area/Austin/Boston·Posted 2mo ago
llm
<p><strong>What We’re Looking For:</strong></p> <p> </p> <p>We’re looking for an architect to own the logical architecture for the A-0 and A-1 wafer products. You will work with the XPU/Compute chip architect and the memory architect to synthesize the final wafer-level architecture. </p> <p> </p> <p><strong>Ideal Background:</strong></p> <p> </p> <p>An ideal candidate will have:</p> <ul> <li>Deep understanding and hands-on experience in the design process of AI chips, such as GPUs, TPUs, XPUs, custom ASICs, etc</li> <li>Understanding of memory sub-systems and interactions in multi-die systems </li> <li>Understanding of LLM inference workloads, especially at a software level and its implications for hardware (system, package, network, die-level) systems </li> </ul> <p><br><br></p> <p><strong>Strongly Preferred: </strong></p> <ul> <li>Experience with multi-die designs </li> <li>Experience with MCM and chiplet based architectures and architectural partitioning across them </li> <li>Experience in partitioning workloads across multiple chips and chip packages</li> </ul>