Packaging Engineer- Flip Chip

<p>We're seeking experienced engineers to contribute to flip chip package development and assembly processes for advanced semiconductor devices (2.5D/3D/chiplet/fan-out/flip-chip).</p> <p>This spans bump metallurgy, substrate integration, reflow and underfill processes, reliability, failure analysis, and cross-functional support through package and system&nbsp;productization.</p> <p>&nbsp;</p> <p><strong>Core Responsibilities:</strong></p> <ul> <li>Develop and optimize flip chip attach processes including bump formation,</li> </ul> <p>placement, reflow, and underfill for high-performance semiconductor packages.</p> <ul> <li>Define and manage bump metallurgy stacks (e.g., Cu pillar, SnAg, micro-bumps)</li> </ul> <p>and substrate pad finishes for robust interconnect performance.</p> <ul> <li>Drive package integration from die to substrate, ensuring alignment, coplanarity,</li> </ul> <p>and yield optimization.</p> <ul> <li>Evaluate and mitigate assembly risks including warpage, non-wet opens, voiding,</li> </ul> <p>head-in-pillow, and interconnect defects.</p> <ul> <li>Collaborate with substrate vendors, OSATs, and internal teams to define design</li> </ul> <p>rules (pad pitch, bump pitch, keep-outs, stack-ups).</p> <ul> <li>Lead process development for reflow profiles, flux selection, cleaning, and underfill</li> </ul> <p>dispense/cure.</p> <ul> <li>Perform root cause analysis of assembly and reliability failures using cross-</li> </ul> <p>sectioning, SEM, CSAM, and other failure analysis techniques.</p> <ul> <li>Support reliability qualification including thermal cycling, drop, mechanical shock,</li> </ul> <p>and power cycling.</p> <ul> <li>Work cross-functionally with design, reliability, thermal, and manufacturing teams</li> </ul> <p>to ensure robust package performance from concept through high-volume</p> <p>production.</p> <p>&nbsp;</p> <p>&nbsp;</p> <p><strong>Required Technical Skills:</strong></p> <ul> <li>Strong experience in flip chip packaging and assembly processes for</li> </ul> <p>semiconductor devices.</p> <ul> <li>Deep understanding of bumping technologies (solder bumps, Cu pillar, micro-</li> </ul> <p>bumps) and UBM/metallization systems.</p> <ul> <li>Experience with underfill materials, dispense techniques, flow behavior, and cure</li> </ul> <p>processes.</p> <ul> <li>Understanding of thermo-mechanical behavior in flip chip assemblies (CTE</li> </ul> <p>mismatch, warpage, solder fatigue, reliability risks).</p> <ul> <li>Hands-on experience with failure analysis and reliability testing (cross-sections,</li> </ul> <p>SEM, CSAM, thermal cycling).</p> <ul> <li>Ability to work with OSATs and suppliers to develop and transfer assembly</li> </ul> <p>processes into production.</p> <ul> <li>Strong problem-solving skills with ability to debug yield and reliability issues in</li> </ul> <p>manufacturing environments.</p> <p>&nbsp;</p> <p>&nbsp;</p> <p><strong>Preferred / Differentiating Skills:</strong></p> <ul> <li>Experience with III-V packaging, photonics packaging, and precision chip attach.</li> <li>Experience with advanced packaging technologies including 2.5D interposers, 3D</li> </ul> <p>stacking, chiplets, and CoWoS-like architectures.</p> <ul> <li>Familiarity with bill of materials used in photonics packaging such as clear</li> </ul> <p>adhesives and underfills as well as mold compounds and underfills for 2.5D</p> <p>advanced packaging.</p> <ul> <li>Familiarity with fine-pitch micro-bump and hybrid bonding approaches.</li> <li>Experience integrating high-power or high-TDP devices with tight warpage and</li> </ul> <p>thermal constraints.</p> <ul> <li>Exposure to thermo-mechanical modeling or collaboration with simulation teams</li> </ul> <p>for warpage and reliability prediction.</p> <ul> <li>Understanding of system-level interactions (PCB attach, second-level interconnect</li> </ul> <p>reliability).</p>