Volantis·Series A·Raised $88.0M·Funded 25d ago

Packaging Engineer- Bump Interconnect

Hybrid Remote/SF Bay Area/Austin/Boston·Posted 3mo ago

We’re seeking an experienced engineer to lead bump interconnect development for advanced semiconductor devices  (2.5D/3D/chiplet/fan-out).    This role spans ubump and C4 bump metallurgy, RDL design and plating, chip-side and interposer capture pad design rules, OSAT engagement, reliability, failure analysis, and cross-functional support through package and system productization.   Core Responsibilities <ul> <li>Own end-to-end bump interconnect development for both ubump (micro-bump) and C4</li> </ul> processes, including bump formation, and reflow for use with mass reflow, TCB, and LAB chip attach for high-performance semiconductor packages. <ul> <li>Define and own bump metallurgy stacks for ubump (e.g., Cu pillar/SnAg) and C4 (e.g., SAC alloys)</li> </ul> interconnects, including UBM selection and pad finish specifications for both chip-side and interposer capture pads. <ul> <li>Develop and own design rules for bump interconnects including pitch, bump diameter, standoff</li> </ul> height, keep-outs, and land pad geometry for both the chip side and interposer or substrate capture pads. <ul> <li>Lead RDL (redistribution layer) process development including electroplating of Cu RDL traces,</li> </ul> via fills, and pad finishes; define RDL design rules for line/space, via diameter, and layer stack-up to meet electrical and reliability requirements. <ul> <li>Collaborate with OSATs and bumping foundries to qualify ubump and C4 bumping processes,</li> </ul> drive design rule alignment, and manage process transfers into production.   <ul> <li>Evaluate and mitigate bump interconnect assembly risks including non-wet opens, voiding, head-</li> </ul> in-pillow, intermetallic growth, and joint fatigue failures across both ubump and C4 interconnect types. <ul> <li>Perform root cause analysis of assembly and reliability failures using cross-sectioning, SEM,</li> </ul> CSAM, and other failure analysis techniques. <ul> <li>Support reliability qualification including thermal cycling, drop, mechanical shock, and power cycling.</li> </ul> <ul> <li>Work cross-functionally with design, reliability, thermal, and manufacturing teams to ensure</li> </ul> robust package performance from concept through high-volume production.   Required Technical Skills <ul> <li>Strong experience in bump interconnect processes including ubump (Cu pillar, micro-bump) and</li> </ul> C4 bumping for semiconductor devices.   <ul> <li>Deep understanding of bumping metallurgy including UBM stacks, solder alloy systems (SnAg),</li> </ul> intermetallic compound (IMC) formation and growth kinetics, and their impact on joint reliability. <ul> <li>Experience with RDL plating processes including Cu electroplating, photoresist patterning, seed</li> </ul> layer deposition, and associated design rules for line/space, via geometry, and pad stack. <ul> <li>Understanding of thermo-mechanical behavior in bump interconnect assemblies including CTE</li> </ul> mismatch, warpage, solder joint fatigue, and IMC-driven reliability risks for both ubump and C4 configurations. <ul> <li>Hands-on experience with failure analysis and reliability testing (cross-sections, SEM, CSAM,</li> </ul> thermal cycling). <ul> <li>Ability to work with OSATs and suppliers to develop and transfer assembly processes into</li> </ul> production. <ul> <li>Strong problem-solving skills with ability to debug yield and reliability issues in manufacturing</li> </ul> environments.   Preferred / Differentiating Skills <ul> <li>Experience with III-V packaging, photonics packaging, and precision chip attach.</li> <li>Experience with advanced packaging technologies including 2.5D interposers, 3D stacking,</li> </ul> chiplets, and CoWoS-like architectures. <ul> <li>Familiarity with fine-pitch micro-bump and hybrid bonding approaches.</li> <li>Experience integrating high-power or high-TDP devices with tight warpage and thermal</li> </ul> constraints. <ul> <li>Exposure to thermo-mechanical modeling or collaboration with simulation teams for warpage</li> </ul> and reliability prediction. <ul> <li>Understanding of system-level interactions (warpage, second-level interconnect reliability).</li> <li>Deep expertise in bump metallurgy fundamentals including UBM stack design (Ti/Cu, etc.), solder</li> </ul> alloy selection, wetting behavior, and the influence of plating chemistry and process conditions on bump morphology and composition. <ul> <li>Fundamental knowledge of intermetallic compound (IMC) formation, growth kinetics, and phase</li> </ul> behavior in Cu/Sn, Ni/Sn, and Au/Sn systems; understanding of how IMC thickness, morphology, and composition affect joint strength, electromigration resistance, and long-term reliability. Education & Experience: Industry experience in semiconductor packaging with strong emphasis on bump interconnect processes, RDL development, and productization.

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