ASIC Design Engineer
Hybrid Remote/SF Bay Area/Austin/Boston·Posted 2mo ago
node
<p><strong>What We’re Looking For:</strong></p> <p>We’re looking for ASIC design engineers to contribute to and own blocks in the development of the A-0 and A-1 wafer products, across both the XPU, memory chiplet and other dies on the wafer. </p> <p> </p> <p><strong>Ideal Background:</strong></p> <p>An ideal candidate will have: </p> <ul> <li>Hands-on experience with multiple advanced node tapeouts</li> <li>Ownership of ASIC design portion of at least one block in multiple advanced node tapeouts</li> <li>Understanding of PPA improvement and what levers exist for each level of the stack </li> <li>Ability to think creatively about methodology for fast design iterations </li> </ul> <p> </p> <p><strong>Nice to Have:</strong></p> <ul> <li>Hands-on experience with ASIC design process for large die (ideally reticle max) chips </li> <li>Hands-on experience with ASIC design process for AI chips </li> <li>Hands-on experience with multi-die/multi-chiplet/MCM designs </li> </ul>