Advanced Packaging Engineer
Hybrid Remote/SF Bay Area/Austin/Boston·Posted 3mo ago
<p> </p> <p><strong>About the Role</strong></p> <p> </p> <p>You will contribute to and own aspects of the Volantis A-0 and A-1 package. </p> <p>We are interested in both people with package design as well as package process development backgrounds </p> <p>Our end goal has challenges to overcome in warpage, CTE mismatch, thermomechanical aspects, assembly speed and more.</p> <p>We're building a wafer-scale package with both silicon and compound semiconductor dies sitting together at very high TDP.</p> <p>This creates both unique challenges and opportunities.</p> <p>The end result is breaking the memory wall, enabling a new era of AI, and a platform that scales another 1-3 orders of magnitude. </p> <p> </p> <p><strong>What We Look For</strong></p> <ul> <li>Ability to think from first principles about novel problems- not just applying existing solutions outside of their range of application. <ul> <li>What works for 5x reticle platforms may not work for 56x reticle platforms </li> </ul> </li> <li>Design or process development of complex packages </li> </ul> <p> </p> <p><strong>Nice to Have:</strong></p> <ul> <li>Experience with heterogeneous material assemblies</li> <li>Experience with high-TDP packages</li> <li>Experience with compound semiconductor assemblies </li> <li>Experience with co-packaged optics </li> <li>Ability to work with architects to co-design system architecture and package design</li> <li>Experience with interposer platforms such as CoWoS, CoWoS-L, CoWoS-R, EMIB, FoCoS, FoCoS-Bridge, etc</li> <li>Experience with flip-chip integration, especially mass reflow, TCB & LAB</li> <li>Experience with large scale (>50x50mm) substrates</li> </ul> <p> </p> <p><strong>Compensation Package:</strong></p> <p>Competitive Base salary + Significant Equity Stake. </p> <p>You'll be well compensated while also owning a piece of the outcome.</p> <p> </p> <p> </p> <p>California Pay Range:<br>$250K-$400K</p> <p> </p>